World Library  
Flag as Inappropriate
Email this Article
 

65 Nm

The 65 nanometer (65 nm) process is advanced lithographic node used in volume CMOS semiconductor fabrication. Printed linewidths (i.e., transistor gate lengths) can reach as low as 25 nm on a nominally 65 nm process, while the pitch between two lines may be greater than 130 nm.[1] For comparison, cellular ribosomes are about 20 nm end-to-end. A crystal of bulk silicon has a lattice constant of 0.543 nm, so such transistors are on the order of 100 atoms across. By September 2007, Intel, AMD, IBM, UMC, Chartered and TSMC were producing 65 nm chips.

While feature sizes may be drawn as 65 nm or less, the wavelengths of light used for lithography are 193 nm and 248 nm. Fabrication of sub-wavelength features requires special imaging technologies, such as optical proximity correction and phase-shifting masks. The cost of these techniques adds substantially to the cost of manufacturing sub-wavelength semiconductor products, with the cost increasing exponentially with each advancing technology node. Furthermore, these costs are multiplied by an increasing number of mask layers that must be printed at the minimum pitch, and the reduction in yield from printing so many layers at the cutting edge of the technology. For new integrated circuit designs, this factors into the costs of prototyping and production.

Gate thickness, another important dimension, is reduced to as little as 1.2 nm (Intel). Only a few atoms insulate the "switch" part of the transistor, causing charge to flow through it. This undesired effect, leakage, is caused by quantum tunneling. The new chemistry of high-k gate dielectrics must be combined with existing techniques including substrate bias and multiple threshold voltages to prevent leakage from prohibitively consuming power.

IEDM papers from Intel in 2002, 2004, and 2005 illustrate the industry trend that the transistor sizes can no longer scale along with the rest of the feature dimensions (gate width only changed from 220 nm to 210 nm going from 90 nm to 65 nm technologies). However, the interconnects (metal and poly pitch) continue to shrink, thus reducing chip area and chip cost, as well as shortening the distance between transistors, leading to higher performance devices of greater complexity when compared with earlier nodes.

Example: Fujitsu 65 nm process[2][3]

  • Gate length: 30 nm (high-performance) to 50 nm (low-power)
  • Core voltage: 1.0 V
  • 11 Cu interconnect layers using nano-clustering silica as ultralow k dielectric (k=2.25)
  • Metal 1 pitch: 180 nm
  • Nickel silicide source/drain
  • Gate oxide thickness: 1.9 nm (n), 2.1 nm (p)

There are actually two versions of the process: CS200, focusing on high performance, and CS200A, focusing on low power.

Processors using 65 nm manufacturing technology

References

  • Engineering Sample of the "Yonah" core Pentium M, IDF Spring 2005, ExtremeTech


Preceded by
90 nm
CMOS manufacturing processes Succeeded by
45 nm
This article was sourced from Creative Commons Attribution-ShareAlike License; additional terms may apply. World Heritage Encyclopedia content is assembled from numerous content providers, Open Access Publishing, and in compliance with The Fair Access to Science and Technology Research Act (FASTR), Wikimedia Foundation, Inc., Public Library of Science, The Encyclopedia of Life, Open Book Publishers (OBP), PubMed, U.S. National Library of Medicine, National Center for Biotechnology Information, U.S. National Library of Medicine, National Institutes of Health (NIH), U.S. Department of Health & Human Services, and USA.gov, which sources content from all federal, state, local, tribal, and territorial government publication portals (.gov, .mil, .edu). Funding for USA.gov and content contributors is made possible from the U.S. Congress, E-Government Act of 2002.
 
Crowd sourced content that is contributed to World Heritage Encyclopedia is peer reviewed and edited by our editorial staff to ensure quality scholarly research articles.
 
By using this site, you agree to the Terms of Use and Privacy Policy. World Heritage Encyclopedia™ is a registered trademark of the World Public Library Association, a non-profit organization.
 


Copyright © World Library Foundation. All rights reserved. eBooks from Project Gutenberg are sponsored by the World Library Foundation,
a 501c(4) Member's Support Non-Profit Organization, and is NOT affiliated with any governmental agency or department.