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Cannonlake

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Title: Cannonlake  
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Subject: Skylake (microarchitecture), Broadwell (microarchitecture), Bonnell (microarchitecture), Ivy Bridge (microarchitecture), Haswell (microarchitecture)
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Cannonlake

Cannonlake
Predecessor Skylake

Cannonlake (formerly Skymont) is Intel's codename for the 10 nanometer die shrink of Intel's Skylake microarchitecture, expected to be released in 2016. As a die shrink, Cannonlake is a "tick" in Intel's tick-tock execution plan as the next step in semiconductor fabrication.[1]

Cannonlake will be used in conjunction with Intel 200 Series chipsets, also known as Union Point. The platform as a whole will be named Union Bay.[1]

Roadmap

Process nodes beyond that of Cannonlake's 10 nm are not clear,[2] although Intel development documents from Q3 2012 indicates 7 nm node may reach production around 2017, with 5 nm in 2019.[3] In 2009 Intel's former CEO Paul S. Otellini was quoted as saying that silicon is in its last decade as the base material of the CPU,[4] with replacement options such as Indium antimonide or optical computing.

See also

References

  1. ^ a b "Intel's Cannonlake 10nm Microarchitecture is Due For 2016 - Compatible On Union Bay With Union Point PCH". WCCFTech. Retrieved 24 September 2014. 
  2. ^ "Intel forges ahead to 7nm – without the use of EUV lasers - ExtremeTech". ExtremeTech. Retrieved 29 September 2014. 
  3. ^ "Intel Has 5 nm Processors in Sight". tomshardware.com. 2012-09-13. 
  4. ^ "Intel looks beyond silicon for processors past 2017". Apcmag.com. 2009-10-25. 
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