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Power Architecture

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Power Architecture

Power Architecture is a registered trademark for similar, comprising over 40 companies and organizations.

The term "Power Architecture" should not be confused with IBM's different generations of "POWER Instruction Set Architecture" where the former is a broad term including all products based on newer POWER, PowerPC and Cell processors, and the latter is a deprecated instruction set for IBM RISC processors of the 1990s, replaced by the PowerPC/Power ISA derivative of the POWER ISA. Power Architecture is a family name describing processor architecture, software, toolchain, community and end-user appliances and not a strict term describing specific products or technologies.


There can be misunderstanding of the meaning of the terms, POWER, PowerPC and Power Architecture. The following glossary gives brief descriptions of each term, along with links to articles with details.

Term Description
POWER Performance Optimization With Enhanced RISC. An old microprocessor instruction set architecture designed by IBM.
PowerPC Power Performance Computing. A 32/64-bit instruction set for microprocessors derived from the POWER ISA, including some new elements. Designed by the AIM alliance; Apple, IBM and Motorola.
PowerPC-AS PowerPC-Advanced Series. Codename "Amazon". A purely 64-bit variant of PowerPC, including some elements from the POWER2 version of the POWER ISA. Used in IBM's RS64 family processors and newer POWER processors.
POWERn Where n is a number from 1 to 8. A series of high-end microprocessors built by IBM using different combinations of POWER, PowerPC, PowerPC-AS and Power instruction sets.

Main articles: POWER processors, POWER1, POWER2, POWER3, POWER4, POWER5, POWER6, POWER7 and POWER8

Cell Cell Broadband Engine Architecture (CBEA), a microprocessor architecture designed by IBM, Sony and Toshiba, which has Power Architecture as a part.
Power Architecture The broad term designating all that is POWER, PowerPC and Cell including software, toolchain and end-user appliances. These are the focus of this article.
Power ISA A new instruction set, combining late versions of POWER and PowerPC instruction sets. Designed by IBM and Freescale.


A schematic showing the evolution of the different POWER, PowerPC and Power ISAs

Power Architecture originated at IBM in the late 1980s when that company wanted a high-performance RISC architecture for their mid-range workstations and servers. The result was the "POWER architecture". Its first implementation featured in the RS/6000 computers introduced in 1990. This was the 10-chip RIOS-1 processor, later called POWER1. The RISC Single Chip (RSC) processor was developed from RIOS-1.

In 1992 Apple, IBM and Motorola formed the AIM alliance to develop a mass-market version of the POWER processor. This resulted in the "PowerPC architecture", a modified version of the POWER architecture. The first PowerPC implementation was the PowerPC 601 of 1993. Based heavily on RSC, it found its way into Apple's Power Mac computers as well as into IBM RS/6000 systems. The differences between the POWER instruction set and PowerPC is outlined in Appendix E of the manual for PowerPC ISA v.2.02.[1]

IBM expanded their POWER architecture for their RS/6000 systems, which resulted in the eight-chip POWER2 processor in 1993 and in a single-chip version called P2SC, "POWER2 Super Chip", in 1996.

In the early 1990s IBM sought to replace its CISC-based AS/400 minicomputers with a RISC architecture. This new architecture, developed under the code name "Amazon", came to be referred to as the PowerPC-AS ("Advanced Series" or "Amazon Series") amongst engineers working on the project. PowerPC-AS was to be a multi-processor server platform based on RSC. As development continued at IBM Research labs to extend RSC to support a 64-processor inter-connect and to add features specific to AS/400, RS/6000 developers joined in and added some POWER2 features. It all ended up with the 64-bit A10 and A30 processors introduced in 1995 and with the later RS64 line in 1997, used in AS/400 and RS/6000 systems.

The AIM Alliance continued to develop PowerPC from 1995 through 1997 and released the second-generation PowerPC processors: The PowerPC 602 for set-top boxes and game consoles; the PowerPC 603 geared towards the embedded market and portable computers; the PowerPC 604 for workstations; and PowerPC 620, a 64-bit high-performance processor for servers. The 602 and 620 never found widespread use, but the 603, 604 and their successors became very popular in their respective fields. Motorola and IBM also made the "Book E"[2] extension of PowerPC, used in embedded implementations: Motorola's PowerQUICC processors and IBM's PowerPC 400 family.

The last effort of the AIM Alliance was the third generation PowerPC 750 in 1997. Motorola and IBM went their separate ways in developing the PowerPC architecture after that. The "G3" processors found widespread use in both computer and embedded markets and IBM kept evolving the 750 family in the years to come. Motorola, however, chose to focus on the embedded market with PowerPC SoC designs and the PowerPC 7400, which they called the fourth generation PowerPC. This processor incorporated AltiVec, a SIMD unit. The "PowerPC G4" came in 1999 and was used by Apple in workstations and laptops and by various companies in the telecom market.

In 1998 came POWER3, which unified the PowerPC and POWER2 architectures but was only used in IBM's RS/6000 servers.

2000 saw the last implementation of the PowerPC-AS architecture, the RS64-IV, used in the AS/400 and in the RS/6000, now renamed the eServer iSeries and the eServer pSeries respectively. IBM also produced the Gekko processor - based on the PowerPC 750CXe - for use in Nintendo's GameCube game console. IBM built the Rivina, experimental 64-bit PowerPC processor, which became the first microprocessor to surpass the 1 GHz mark.

In 2001 IBM introduced the POWER4, which unified and replaced the PowerPC-AS and POWER3 architectures.

In 2002 Apple desperately needed a new high-end PowerPC part and got IBM to make the 64-bit PowerPC 970. Apple described it as the fifth-generation PowerPC or "G5". The PowerPC 970 derives from POWER4. It lacks some server-oriented features, but does have an AltiVec unit. The 970 and its descendants are used by Apple and IBM and some high-end embedded applications.

In 2003 Tundra Semiconductor bought the PowerPC 100 family of microcontrollers from Motorola, while Culturecom licensed PowerPC technology from IBM for their V-Dragon processor.

The Power Architecture logo in the shape of a Möbius strip.

Motorola spun off its semiconductor division into a new company called [6]

2005 saw the specifications of the Cell processor,[7] jointly developed by IBM, Sony and Toshiba over a four-year period. Its primary use is for Sony's PlayStation 3. Cell uses a single 64-bit Power Architecture core, and adds 8 independent SIMD cores called SPEs. IBM also revealed the Xenon processor, a tri-core 64-bit processor for use in Microsoft's Xbox 360. With the 32-bit PowerPC based Broadway processor that Nintendo would use for its Wii console, IBM had put Power Architecture processors in all three of the major seventh-generation game consoles.

P.A. Semi licensed Power Architecture technology from IBM for use in its PWRficient processors.

Freescale joined in 2006 and IBM made the specifications of PowerPC 405 freely available to researchers and to academia. released the Power ISA version 2.03.[8] in September 2006. All previous PowerPC specifications are compatible with the 64-bit Power ISA. This added, among other things, VMX, virtualization and variable-length encoding (VLE, 2-byte instructions added to previously 4-byte instructions) to the specification. released the Power Architecture Platform Reference, PAPR, in the fourth quarter of 2006. It provided the foundation for development of computers based on Power Architecture-based using the Linux operating system.

In April 2007, Freescale and IPextreme opened up a licensing program for Freescale's [10] specification in June 2007. Improvements focused mainly on server applications and virtualization. At the Power Architecture Developer Conference in September 2007, drafts to Power ISA v.2.05 and ePAPR specification were shown, and a Linux-based reference design based on PowerPC 970MP was revealed.[11] The Power ISA v.2.05 specification was released in December 2007.[12]

In April 2008, IBM rebranded their Power Architecture-based hardware, System p and System i. They are now called "Power Systems". At the same time IBM rebranded the i5/OS operating system as "IBM i". On May 25, 2008, IBM became the first vendor to break the 1 Petaflops barrier with the Roadrunner supercomputer.[13] In June 2008 Roadrunner entered the Top500 list of the fastest computers in the world in first place, replacing the BlueGene/L which had held that position since November 2004. On June 16, 2008, Freescale announced QorIQ families P1, P2, P3, P4 and P5, the evolution of PowerQUICC, featuring the eight-core P4080.[14]

According to the June 2008 TOP500 list, the third- and sixth-fastest supercomputers in the world, and 22 of the 50 fastest supercomputers, used IBM's technologies based on Power Architecture. Of the top ten, five used Power Architecture processors as computing elements and one used them as communications processors.

In September 2008, a new supercomputer, Blue Waters, originally intended to be POWER7-based, got the green light.[15] For a cost of $208 million, it will contain 200,000 processors, bringing multi-petaflops performance in 2010-2011. In December 2008, the ePAPR v.1.0 specification for embedded computers based on Power Architecture was finalized.[16] In 2011 IBM dropped out of the project;[17] Cray Research provided the actual processors used.[18]

The Power ISA v.2.06 specification was released in February 2009,[19] and revised in July 2010.[20] Mentor Graphics enables the Android mobile operating system on Freescale's QorIQ and PowerQUICC III platforms in July 2009.[21]

At the ISSCC 2010 conference in February 2010 IBM released the POWER7 processor and revealed the PowerPC A2 "wire-speed processor" - both massively multicore and multithreaded server-oriented processors comprising over 1 billion transistors each. In June Freescale announced their first 64-bit core, the e5500, implemented in the QorIQ P5 family processors.[22]

Freescale announced the multithreaded 64-bit e6500 core in June 2011 under the QorIQ AMP brand. It will reintroduce AltiVec SIMD units into Freescale's offerings, and be integrated in multiple products manufactured in a 28 nm process beginning 2012.[23]

At the E3 trade show in June 2011 Nintendo announced the Wii U game console, which uses a multicore Power Architecture processor of unknown characteristics, designed and manufactured by IBM.[24]

In August 2013 IBM founded the OpenPOWER Foundation, an initiative to spur innovation and collaboration in the server and data-center space, opening up for licensing of their future POWER8 processor and related technologies. They also revealed the POWER8 processor itself, manufactured on a 22 nm process, with 12 eight-way multithreaded cores running at 4 GHz.

IBM released servers based on POWER8 in June 2014,[25] and Tyan, a founding member of the OpenPOWER Foundation, released the first third-party POWER8 in October 2014.[26]


The Power Architecture is open for licensing by third parties. Licensees can choose to license anything from a single predefined core, to a complete new family of Power Architecture products.

IBM licenses hard (predefined chip designs) and soft (synthesized design that can be used in different foundries) core implementations of both the 32-bit and 64-bit Power Architecture, either directly or through Power Design Center partners such as HCL Technologies or Synopsys. On a strategic basis, IBM also provide both microarchitecture and architecture licenses. A microarchitecture license enables licensees to implement a new pipeline for a core, but not to add or subtract instructions from the Power Instruction Set Architecture (ISA). Microarchitecture licenses cover both 64-bit and 32-bit, although individual licenses are available if necessary/desired.

IBM has announced plans to make the specifications of the PowerPC 405 core freely available to the academic and research community.

In April 2007 Freescale and IPextreme opened up the PowerPC e200 cores for licensing to other manufacturers.[9]

Companies that have developed or are developing their own processors based on the Power Architecture under license include Tundra Semiconductor, Applied Micro Circuits Corporation, HCL Enterprise, Culturecom, P.A. Semi, Xilinx, Microsoft, Rapport, Sony, Honeywell, Toshiba and Cray.


Power Architecture
Bits 32-bit/64-bit (32 → 64)
Introduced 2006
Version 2.07
Design RISC
Type Register-Register
Encoding Fixed/Variable
Branching Condition code
Endianness Big/Bi
Extensions AltiVec, APU, DSP, CBEA
Open Yes
  • 32× 64/32-bit general purpose registers
  • 32× 64-bit floating point registers
  • 32× 128-bit vector registers
  • 32-bit condition code register
  • 32-bit link register
  • 32-bit count register
+ more
A highly schematic diagram over a generic Power Architecture processor.

The instruction set architecture is divided into several categories and every component is defined as a part of a category; each category resides within a certain Book. Processors implement a set of these categories. Different classes of processors are required to implement certain categories, for example a server class processor includes the categories Base, Server, Floating-Point, 64-Bit, etc. All processors implement the Base category.

Power is a RISC load/store architecture. It has multiple sets of registers:

  • thirty-two 32-bit or 64-bit general purpose registers (GPRs) for integer operations.
  • sixty-four 128-bit vector scalar registers (VSRs) for vector operations and floating point operations.
    • thirty-two 64-bit floating-point registers (FPRs) as part of the VSRs for floating point operations.
    • thirty-two 128-bit vector registers (VRs) as part of the VSRs for vector operations.
  • Eight 4-bit condition register fields (CRs) for comparison and control flow.
  • Special registers: counter register (CTR), link register (LR), time base (TBU, TBL), alternate time base (ATBU, ATBL), accumulator (ACC), status registers (XER, FPSCR, VSCR, SPEFSCR).

Instructions have a length of 32 bits, with the exception of the VLE (variable-length encoding) subset that provides for higher code density for low-end embedded applications. Most instructions are triadic, i.e. have two source operands and one destination. Single and double precision IEEE-754 compliant floating point operations are supported, including additional fused multiply–add (FMA) and decimal floating-point instructions. There are provisions for SIMD operations on integer and floating point data on up to 16 elements in a single instruction.

Support for Harvard cache, i.e. split data and instruction caches, as well as support for unified caches. Memory operations are strictly load/store, but allow for out-of-order execution. Support for both big and little-endian addressing with separate categories for moded and per-page endianness. Support for both 32-bit and 64-bit addressing.

Different modes of operation include user, supervisor and hypervisor.


  • Base – Most of Book I and Book II
  • Server – Book III-S
  • Embedded – Book III-E
  • Misc – floating point, vector, signal processing, cache locking, decimal floating point, etc.


The Power Architecture specification is divided into five parts, called "books":

  • Book IUser Instruction Set Architecture covers the base instruction set available to the application programmer. Memory reference, flow control, Integer, floating point, numeric acceleration, application-level programming. It includes chapters regarding auxiliary processing units like DSPs and the AltiVec extension.
  • Book IIVirtual Environment Architecture defines the storage model available to the application programmer, including timing, synchronization, cache management, storage features, byte ordering.
  • Book IIIOperating Environment Architecture includes exceptions, interrupts, memory management, debug facilities and special control functions. It's divided into two parts.
    • Book III-S – Defines the supervisor instructions used for general purpose/server implementations. It is mainly the contents of the Book III of the former PowerPC ISA.
    • Book III-E – Defines the supervisor instructions used for embedded applications. It is derived from the former PowerPC Book E.
  • Book VLEVariable Length Encoded Instruction Architecture defines alternative instructions and definitions from Book I-III, intended for higher instruction density and very-low-end applications. They use 16-bit instructions and big endian byte ordering.


Power ISA v.2.03

The specification for Power ISA v.2.03[8] is based on the former PowerPC ISA v.2.02[4] in POWER5+ and the Book E[2] extension of the PowerPC specification. The Book I included five new chapters regarding auxiliary processing units like DSPs and the AltiVec extension.

Compliant cores

Power ISA v.2.04

The specification for Power ISA v.2.04[10] was finalized in June 2007. It is based on Power ISA v.2.03 and includes changes primarily to the Book III-S part regarding virtualization, hypervisor functionality, logical partitioning and virtual page handling.

Compliant cores

  • All cores that comply with previous versions of the Power ISA
  • The PA6T core from P.A. Semi
  • Titan from AMCC

Power ISA v.2.05

The specification for Power ISA v.2.05[12] was released in December 2007. It is based on Power ISA v.2.04 and includes changes primarily to Book I and Book III-S, including significant enhancements such as decimal arithmetic (Category: Decimal Floating-Point in Book I) and server hypervisor improvements.

Compliant cores

Power ISA v.2.06

The specification for Power ISA v.2.06[11][19] was released in February 2009, and revised in July 2010.[20] It is based on Power ISA v.2.05 and includes extensions for the POWER7 processor and e500-mc core. One significant new feature is vector-scalar floating-point instructions (VSX). Book III-E also includes significant enhancement for the embedded specification regarding hypervisor and virtualisation on single and multi core implementations.

The spec was revised in November 2010 to the Power ISA v.2.06 revision B spec, enhancing virtualization features.[27]

Compliant cores

Power ISA v.2.07

The specification for Power ISA v.2.07[28] was released in May 2013. It is based on Power ISA v.2.06 and includes major enhancements to logical partition functionality, transactional memory, expanded performance monitoring, new storage control features, additions to the VMX and VSX vector facilities and crypto operations.

The spec was revised in April 2015 to the current Power ISA v.2.07 B spec.[29]

Compliant cores

  • All cores that comply with previous versions of the Power ISA
  • POWER8
  • e6500 core




  • Printers, cars, aircraft, medical imaging, telecom equipment, spacecraft, RIPs, set top boxes, etc., from a multitude of companies.

Operating systems


  1. ^ PowerPC User Instruction Set Architecture Book I, version 2.02
  2. ^ a b
  3. ^
  4. ^ a b
  5. ^
  6. ^
  7. ^
  8. ^ a b
  9. ^ a b
  10. ^ a b
  11. ^ a b
  12. ^ a b
  13. ^
  14. ^
  15. ^ [1]
  16. ^
  17. ^
  18. ^
  19. ^ a b
  20. ^ a b
  21. ^
  22. ^
  23. ^
  24. ^
  25. ^ IBM Tackles Big Data Challenges with Open Server Innovation Model
  26. ^ Tyan Ships First Non-IBM Power8 Server
  27. ^
  28. ^
  29. ^
  30. ^ a b c These operating systems have been completely discontinued
  31. ^
  32. ^ a b c d These operating systems are discontinued on Power Architecture
  33. ^

External links

  • 27 years of IBM RISC
  • POWER to the people – A history of chipmaking at IBM
  • Power Architecture Primer
  • PowerPC transition to Power Architecture Guidelines
  • IBM's Power Architecture site
  • Freescale's Power Architecture site
  • Applied Micro's embedded processor site
  • Mercury's Cell BE site
  • Integrated Device Technology Serial RapidIO® Solutions
  • Genesi's homepage
  • Linux/PPC homepage
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