World Library  
Flag as Inappropriate
Email this Article


Article Id: WHEBN0000041425
Reproduction Date:

Title: Non-return-to-zero  
Author: World Heritage Encyclopedia
Language: English
Subject: Line code, Return-to-zero, Delay encoding, Astrionics, Pulse shaping
Publisher: World Heritage Encyclopedia


The binary signal is encoded using rectangular pulse amplitude modulation with polar non-return-to-zero code

In telecommunication, a non-return-to-zero (NRZ) line code is a binary code in which ones are represented by one significant condition, usually a positive voltage, while zeros are represented by some other significant condition, usually a negative voltage, with no other neutral or rest condition. The pulses in NRZ have more energy than a return-to-zero (RZ) code, which also has an additional rest state beside the conditions for ones and zeros. NRZ is not inherently a self-clocking signal, so some additional synchronization technique must be used for avoiding bit slips; examples of such techniques are a run length limited constraint and a parallel synchronization signal.

For a given data signaling rate, i.e., bit rate, the NRZ code requires only half the baseband bandwidth required by the Manchester code (the passband bandwidth is the same). When used to represent data in an asynchronous communication scheme, the absence of a neutral state requires other mechanisms for bit synchronization when a separate clock signal is not available.

NRZ-Level itself is not a synchronous system but rather an encoding that can be used in either a synchronous or asynchronous transmission environment, that is, with or without an explicit clock signal involved. Because of this, it is not strictly necessary to discuss how the NRZ-Level encoding acts "on a clock edge" or "during a clock cycle" since all transitions happen in the given amount of time representing the actual or implied integral clock cycle. The real question is that of sampling—the high or low state will be received correctly provided the transmission line has stabilized for that bit when the physical line level is sampled at the receiving end.

However, it is helpful to see NRZ transitions as happening on the trailing (falling) clock edge in order to compare NRZ-Level to other encoding methods, such as the mentioned Manchester code, which requires clock edge information (is the XOR of the clock and NRZ, actually) see the difference between NRZ-Mark and NRZ-Inverted.

Unipolar non-return-to-zero level

Unipolar non-return-to-zero level

"One" is represented by a DC bias on the transmission line (conventionally positive), while "zero" is represented by the absence of bias - the line at 0 volts or grounded. For this reason it is also known as "on-off keying." In clock language, a "one" transitions to or remains at a biased level on the trailing clock edge of the previous bit, while "zero" transitions to or remains at no bias on the trailing clock edge of the previous bit. Among the disadvantages of unipolar NRZ is that it allows for long series without change, which makes synchronization difficult - although this is not unique to the unipolar case. One solution is to not send bytes without transitions. More critically, and unique to unipolar NRZ, are issues related to the presence of a transmitted DC level - the power spectrum of the transmitted signal does not approach zero at zero frequency. This leads to two significant problems - first, the transmitted DC power leads to higher power losses than other encodings and second, the presence of a DC signal component requires that the transmission line be DC coupled.

Bipolar non-return-to-zero level

"One" is represented by one physical level (usually a positive voltage), while "zero" is represented by another level (usually a negative voltage). In clock language, in bipolar NRZ-Level the voltage "swings" from positive to negative on the trailing edge of the previous bit clock cycle.

An example of this is RS-232, where "one" is −12 V to −5 V and "zero" is +5 V to +12 V.

}#invoke:anchor|main}}Non-return-to-zero space

Non-return-to-zero space

"One" is represented by no change in physical level, while "zero" is represented by a change in physical level. In clock language, the level transitions on the trailing clock edge of the previous bit to represent a "zero".

This "change-on-zero" is used by High-Level Data Link Control and USB. They both avoid long periods of no transitions (even when the data contains long sequences of 1 bits) by using zero-bit insertion. HDLC transmitters insert a 0 bit after five contiguous 1 bits (except when transmitting the frame delimiter '01111110'). USB transmitters insert a 0 bit after six consecutive 1 bits. The receiver at the far end uses every transition — both from 0 bits in the data and these extra non-data 0 bits — to maintain clock synchronization. The receiver otherwise ignores these non-data 0 bits.

}#invoke:anchor|main}}Non-return-to-zero inverted

An example of the NRZI encoding
NRZ transition occurs for a zero

Non return to zero, inverted (NRZI) is a method of mapping a binary signal to a physical signal for transmission over some transmission media. The two level NRZI signal has a transition at a clock boundary if the bit being transmitted is a logical 1, and does not have a transition if the bit being transmitted is a logical 0.

"One" is represented by a transition of the physical level, while "zero" has no transition. Also, NRZI might take the opposite convention, as in Universal Serial Bus (USB) signalling, when in Mode 1, in which a transition occurs when signaling zero, and a steady level when signaling a one. The transition occurs on the leading edge of the clock for the given bit. This distinguishes NRZI from NRZ-Mark.

However, even NRZI can have long series of zeros (or ones if transitioning on "zero"), and thus clock recovery can be difficult unless some form of run length limited (RLL) coding is used in addition to NRZI. Magnetic disk and tape storage devices generally use fixed-rate RLL codes, while USB uses bit stuffing, which inserts an additional 0 bit after 6 consecutive 1 bits, thus forcing a transition. While bit stuffing is efficient, it results in a variable data rate because it takes slightly longer to send a long string of 1 bits than it does to send a long string of 0 bits.

See also

}}}}}}} | {{#if:Non return to zero

| | 1=Category:Non return to zero


  • Brey, Barry. The Intel Microprocessors, Columbus: Pearson Prentice Hall. ISBN 0-13-119506-9

 This article incorporates public domain material from the General Services Administration document "Federal Standard 1037C" (in support of MIL-STD-188).

This article was sourced from Creative Commons Attribution-ShareAlike License; additional terms may apply. World Heritage Encyclopedia content is assembled from numerous content providers, Open Access Publishing, and in compliance with The Fair Access to Science and Technology Research Act (FASTR), Wikimedia Foundation, Inc., Public Library of Science, The Encyclopedia of Life, Open Book Publishers (OBP), PubMed, U.S. National Library of Medicine, National Center for Biotechnology Information, U.S. National Library of Medicine, National Institutes of Health (NIH), U.S. Department of Health & Human Services, and, which sources content from all federal, state, local, tribal, and territorial government publication portals (.gov, .mil, .edu). Funding for and content contributors is made possible from the U.S. Congress, E-Government Act of 2002.
Crowd sourced content that is contributed to World Heritage Encyclopedia is peer reviewed and edited by our editorial staff to ensure quality scholarly research articles.
By using this site, you agree to the Terms of Use and Privacy Policy. World Heritage Encyclopedia™ is a registered trademark of the World Public Library Association, a non-profit organization.

Copyright © World Library Foundation. All rights reserved. eBooks from Project Gutenberg are sponsored by the World Library Foundation,
a 501c(4) Member's Support Non-Profit Organization, and is NOT affiliated with any governmental agency or department.