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Programmable read-only memory

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Title: Programmable read-only memory  
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Programmable read-only memory

A programmable read-only memory (PROM) or field programmable read-only memory (FPROM) or one-time programmable non-volatile memory (OTP NVM) is a form of digital memory where the setting of each bit is locked by a fuse or antifuse. They are a type of ROM (read-only memory) meaning the data in them is permanent and cannot be changed. PROMs are used in digital electronic devices to store permanent data, usually low level programs such as firmware (microcode). The key difference from a standard ROM is that the data is written into a ROM during manufacture, while with a PROM the data is programmed into them after manufacture. So ROMs are used only for large production runs, while PROMs are used for smaller production where the program may have to be changed.

PROMs are manufactured blank and, depending on the technology, can be programmed at wafer, final test, or in system. Blank PROM chips are programmed by plugging them into a device called a PROM programmer. The availability of this technology allows companies to keep a supply of blank PROMs in stock, and program them at the last minute to avoid large volume commitment. These types of memories are frequently used in microcontrollers, video game consoles, mobile phones, radio-frequency identification (RFID) tags, implantable medical devices, high-definition multimedia interfaces (HDMI) and in many other consumer and automotive electronics products.


The PROM was invented in 1956 by Wen Tsing Chow, working for the Arma Division of the American Bosch Arma Corporation in Garden City, New York. The invention was conceived at the request of the United States Air Force to come up with a more flexible and secure way of storing the targeting constants in the Atlas E/F ICBM's airborne digital computer. The patent and associated technology was held under secrecy order for several years while the Atlas E/F was the main operational missile of the United States ICBM force. The term "burn," referring to the process of programming a PROM, is also in the original patent, as one of the original implementations was to literally burn the internal whiskers of diodes with a current overload to produce a circuit discontinuity. The first PROM programming machines were also developed by Arma engineers under Mr. Chow's direction and were located in Arma's Garden City lab and Air Force Strategic Air Command (SAC) headquarters.

Commercially available semiconductor antifuse-based OTP memory arrays have been around at least since 1969, with initial antifuse bit cells dependent on blowing a capacitor between crossing conductive lines. Texas Instruments developed a MOS gate-oxide breakdown antifuse in 1979.[1] A dual-gate-oxide two-transistor (2T) MOS antifuse was introduced in 1982.[2] Early oxide breakdown technologies exhibited a variety of scaling, programming, size and manufacturing problems that prevented volume production of memory devices based on these technologies.

Although antifuse OTP has been available for decades, it wasn’t available in standard CMOS until 2001 when Kilopass Technology Inc. patented 1T, 2T, and 3.5T antifuse bit cell technologies using a standard CMOS process, enabling integration of PROM into logic CMOS chips. The first process node antifuse can be implemented in standard CMOS is 0.18 um. Since the Gox breakdown is less than the junction breakdown, special diffusion steps were not required to create the antifuse programming element. In 2005, a split channel antifuse device[3] was introduced by Sidense. This Split Channel bit cell combines the thick (IO) and thin (gate) oxide devices into one transistor (1T) with a common polysilicon gate.


A typical PROM comes with all bits reading as "1". Burning a fuse bit during programming causes the bit to read as "0". The memory can be programmed just once after manufacturing by "blowing" the fuses, which is an irreversible process. Blowing a fuse opens a connection while programming an antifuse closes a connection (hence the name). While it is impossible to "unblow" the fuses, it is often possible to change the contents of the memory after initial programming by blowing additional fuses, changing some remaining "1" bits in the memory to "0"s. (Once all of the bits are "0", no further programming change is possible.)

The bit cell is programmed by applying a high-voltage pulse not encountered during normal operation across the gate and substrate of the thin oxide transistor (around 6V for a 2 nm thick oxide, or 30MV/cm) to break down the oxide between gate and substrate. The positive voltage on the transistor’s gate forms an inversion channel in the substrate below the gate, causing a tunneling current to flow through the oxide. The current produces additional traps in the oxide, increasing the current through the oxide and ultimately melting the oxide and forming a conductive channel from gate to substrate. The current required to form the conductive channel is around 100µA/100nm2 and the breakdown occurs in approximately 100µs or less.[4]


  1. ^ See US Patent 4184207 - High density floating gate electrically programmable ROM, and US Patent 4151021 - Method of making a high density floating gate electrically programmable ROM
  2. ^ Chip Planning Portal. Retrieved on 2013-08-10.
  3. ^ See US Patent 7402855 split channel antifuse device
  4. ^


  • View the US "Switch Matrix" Patent #3028659 at US Patent Office or Google
  • View Kilopass Technology Patent US "High density semiconductor memory cell and memory array using a single transistor and having variable gate oxide breakdown" Patent #6940751 at US Patent Office or Google
  • View Sidense US "Split Channel Antifuse Array Architecture" Patent #7402855 at US Patent Office or Google
  • View the US "Method of Manufacturing Semiconductor Integrated Circuits" Patent #3634929 at US Patent Office or Google
  • CHOI et al. (2008). "New Non-Volatile Memory Structures for FPGA Architectures"
  • For the Advantages and Disadvantages table, see Ramamoorthy, G: "Dataquest Insight: Nonvolatile Memory IP Market, Worldwide, 2008-2013", page 10. Gartner, 2009
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