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Resistive random-access memory

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Title: Resistive random-access memory  
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Subject: Memristor, Computer memory, Flash memory, Williams tube, EEPROM
Collection: Computer Memory, Emerging Technologies, Non-Volatile Memory, Solid-State Computer Storage Media, Types of Ram
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Resistive random-access memory

Resistive random-access memory (RRAM or ReRAM) is a type of non-volatile (NV) random-access (RAM) computer memory that works by changing the resistance across a dielectric solid-state material often referred to as a memristor. This technology bears some similarities to CBRAM and phase-change memory (PCM).

CBRAM involves one electrode providing ions which dissolve readily in an electrolyte material, while PCM involves generating sufficient Joule heating to effect amorphous-to-crystalline or crystalline-to-amorphous phase changes. On the other hand, RRAM involves generating defects in a thin oxide layer, known as oxygen vacancies (oxide bond locations where the oxygen has been removed), which can subsequently charge and drift under an electric field. The motion of oxygen ions and vacancies in the oxide would be analogous to the motion of electrons and holes in a semiconductor.

RRAM is currently under development by a number of companies, some of which have filed patent applications claiming various implementations of this technology.[1][2][3][4][5][6][7] RRAM has entered commercialization on an initially limited KB-capacity scale.[8]

Although commonly anticipated as a replacement technology for flash memory, the cost benefit and performance benefit of RRAM have not been obvious enough to most companies to proceed with the replacement. A broad range of materials apparently can potentially be used for RRAM. However, the recent discovery [9] that the popular high-k gate dielectric HfO2 can be used as a low-voltage RRAM has greatly encouraged others to investigate other possibilities.


  • History 1
  • Forming 2
  • Operation Styles 3
  • Material systems for resistive memory cells 4
  • Demonstrations 5
  • Future applications 6
  • References 7


In February 2012 Rambus bought a RRAM company called Unity Semiconductor for $35 million.[10] Panasonic launched a RRAM evaluation kit in May 2012, based on a tantalum oxide 1T1R (1 transistor – 1 resistor) memory cell architecture.[11]

In 2013, Crossbar introduced an RRAM prototype as a chip about the size of a postage stamp that could store 1 TB of data. In August 2013, the company claimed that large-scale production of their RRAM chips was scheduled for 2015.[12] The memory structure (Ag/a-Si/Si) closely resembles a silver-based CBRAM.

Different forms of RRAM have been disclosed, based on different dielectric materials, spanning from perovskites to transition metal oxides to chalcogenides. Silicon dioxide was shown to exhibit resistive switching as early as 1967,[13] and has recently been revisited.[14][15]

Leon Chua argued that all two-terminal non-volatile memory devices including RRAM should be considered memristors.[16] Stan Williams of HP Labs also argued that RRAM was a memristor.[17] However, others challenged this terminology by and the applicability of memristor theory to any physically realizable device is open to question.[18][19] Whether redox-based resistively switching elements (RRAM) are covered by the current memristor theory is disputed.[20]

In 2014 researchers announced a device that used a porous silicon oxide dielectric with no edge structure. In 2010 conductive filament pathways were discovered, leading to the later advance. It can be manufactured at room temperature and has a sub-2V forming voltage, higher on-off ratio, lower power consumption, nine-bit capacity per cell, higher switching speeds and improved endurance.[21]


Filament forming:A 50 nm x 50 nm RRAM by Crossbar shows the instance of filament forming when the current abruptly increases beyond a certain voltage. A transistor is often used to limit current to prevent a runaway breakdown following the filament formation.

The basic idea is that a dielectric, which is normally insulating, can be made to conduct through a filament or conduction path formed after application of a sufficiently high voltage. The conduction path can arise from different mechanisms, including vacancy or metal defect migration. Once the filament is formed, it may be RESET(broken, resulting in high resistance) or SET(re-formed, resulting in lower resistance) by another voltage. Many current paths, rather than a single filament, are possibly involved.[22]

The low resistance path can be either localized (filamentary) or homogeneous. Both effects can occur either throughout the entire distance between the electrodes or only in proximity to one of the electrodes. Filamentary and homogenous switching effects can be distinguished by measuring the area dependence of the low resistance state.[23]

Under certain conditions, the forming operation may be bypassed.[24] It is expected that under these conditions, the initial current is already quite high compared to insulating oxide layers.

CBRAM cells generally would not require forming if Cu ions are already present in the electrolyte, having already been driven-in by a designed photo-diffusion or annealing process; such cells may also readily return to their initial state.[25] In the absence of such Cu initially being in the electrolyte, the voltage would still be applied directly to the electrolyte, and forming would be a strong possiblity.[26]

Operation Styles

For random access type memories, a 1T1R (one transistor, one resistor) architecture is preferred because the transistor isolates current to cells which are selected from cells which are not. On the other hand, a cross-point architecture is more compact and may enable vertically stacking memory layers, ideally suited for mass storage devices. However, in the absence of any transistors, isolation must be provided by a 'selector' device, such as a diode, in series with the memory element, or by the memory element itself. Such isolation capabilities are inferior to the use of transistors if the on/off ratio for the selector is not sufficient, limiting the ability to operate very large arrays in this architecture. Thin film based threshold switch can work as a selector for bipolar and unipolar RRAM. Threshold switch-based selector was demonstrated for 64Mb array [27]

Polarity can be either binary or unary. Bipolar effects cause polarity to reverse when switching from low to high resistance (reset operation) compared to switching high to low (set operation). Unipolar switching leaves polarity unaffected, but uses different voltages.

Material systems for resistive memory cells

Multiple inorganic and organic material systems display thermal or ionic resistive switching effects. These can be grouped into the following categories:[23]

  • phase change chalcogenides such as Ge
    or AgInSbTe
  • binary transition metal oxides such as NiO or TiO
  • perovskites such as Sr(Zr)TiO
    or PCMO
  • solid-state electrolytes such as GeS, GeSe, SiO
    or Cu
  • organic charge transfer complexes such as CuTCNQ
  • organic donor–acceptor systems such as Al AIDCN


Papers at the IEDM Conference in 2007 suggested for the first time that RRAM exhibits lower programming currents than PRAM or MRAM without sacrificing programming performance, retention or endurance.[28] On April 30, 2008 HP announced that they had discovered the memristor, originally envisioned as a missing 4th fundamental circuit element by Chua in 1971. On July 8 they announced they would begin prototyping RRAM using their memristors.[29] At IEDM 2008, the highest performance RRAM technology to date was demonstrated by ITRI, showing switching times less than 10 ns and currents less than 30 microamps. At IEDM 2010, ITRI again broke the speed record, showing <0.3 ns switching time, while also showing process and operation improvements to allow yield up to 100%.[30] IMEC presented updates of their RRAM program at the 2012 Symposia on VLSI Technology and Circuits, including a solution with a 500nA operating current.[31]

Future applications

Compared to PRAM, RRAM operates at a faster timescale (switching time can be less than 10 ns), while compared to MRAM, it has a simpler, smaller cell structure (less than 8F² MIM stack). A vertical 1D1R (one diode, one resistive switching device) integration can be used for crossbar memory structure to reduce the unit cell size to 4F² (F is the feature dimension).[32] Compared to flash memory and racetrack memory, a lower voltage is sufficient and hence it can be used in low power applications.

ITRI has shown that RRAM is scalable below 30 nm.[33] The motion of oxygen atoms is a key phenomenon for oxide-based RRAM;[34] one study indicated that oxygen motion may take place in regions as small as 2 nm.[35] It is believed that if a filament is responsible, it would not exhibit direct scaling with cell size.[36] Instead, the current compliance limit (set by an outside resistor, for example) could define the current-carrying capacity of the filament.[37]

A significant hurdle to realizing the potential of RRAM is the sneak path problem that occurs in larger passive arrays. In 2010, complementary resistive switching (CRS) was introduced as a possible solution to sneak-path current interference.[38] In the CRS approach, the information storing states are pairs of high and low resistance states (HRS/LRS and LRS/HRS) so that the overall resistance is always high, allowing for larger passive crossbar arrays.

A drawback to the initial CRS solution is the requirement for switching endurance caused by conventional destructive readout based on current measurements. A new approach for a nondestructive readout based on capacity measurement potentially lowers the requirements for both material endurance and power consumption.[39] Bi-layer structure is used to produce the nonlinearity in LRS to avoid the sneak path problem.[40] A single layer device exhibiting a strong nonlinear conduction in LRS was reported.[41] Another bi-layer structure was introduced for bipolar RRAM to improve the HRS and stability.[42]

Another solution to the sneak current issue is to perform READ and RESET operations in parallel across an entire row of cells, while using SET on selected cells.[43] In this case, for a 3D-RRAM 1TNR array, with a column of N RRAM cells situated above a select transistor, only the intrinsic nonlinearity of the HRS is required to be sufficiently large, since the number of vertical levels N is limited (e.g., N = 8 − 32), and this has been shown possible for a low-current RRAM system.[44]


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