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Wdc 65c02

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Title: Wdc 65c02  
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Subject: Comparison of assemblers, BBC Master, Hudson Soft HuC6280, Acorn MOS, List of home computers
Collection: 65Xx Microprocessors
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Wdc 65c02

The Western Design Center (WDC) 65C02 microprocessor is an enhanced CMOS version of the popular NMOS-based MOS Technology 6502 8-bit microprocessor—the CMOS redesign being made by Bill Mensch in 1978. Over various periods of time, the 65C02 has been second-sourced by NCR, GTE, Rockwell, Synertek and Sanyo. The 65C02 has been used in some home computers, as well as in embedded applications, including medical-grade implanted devices.
W65C02S microprocessor in a PDIP-40 package.


  • Introduction and features 1
    • General logic features 1.1
    • Logic specifics 1.2
    • Electrical features 1.3

Introduction and features

The 65C02 is a low cost, general-purpose 8-bit microprocessor (8-bit registers and data bus) with a 16-bit program counter and address bus. The variable length instruction set and manually optimized core size are intended to make the 65C02 well suited for low power system-on-chip (SoC) designs.

The W65C02S–14 is the production version of the 65C02 microprocessor, and is available in PDIP, PLCC and QFP packages through distribution. The maximum officially supported Ø2 (primary) clock speed is 14MHz, indicated by the –14 part number suffix. The "S" designation indicates that the part has a fully static core, a feature that allows Ø2 to be slowed down or fully stopped in either the high or low state with no loss of data. Typical microprocessors not implemented in CMOS have dynamic cores and will lose their internal register contents (and thus crash) if they are not continuously clocked at a rate between some minimum and maximum specified values.

A Verilog hardware description model is available for designing the W65C02S core into an application-specific integrated circuit (ASIC) or a field-programmable gate array (FPGA). As is common in the semiconductor industry, WDC offers a development system, which includes a developer board, an in-circuit emulator (ICE) and a software development system.
65C02 registers
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 (bit position)
Main registers
  A Accumulator
Index registers
  X X index
  Y Y index
0 0 0 0 0 0 0 1 SP Stack Pointer
Program counter
PC Program Counter
Status register
  N V - B D I Z C Status Register

General logic features

Logic specifics

  • Vector pull (VPB) output indicates when interrupt vectors are being addressed
  • Memory lock (MLB) output indicates to other bus masters when a read-modify-write instruction is being processed
  • WAit-for-Interrupt (WAI) and SToP (STP) instructions reduce power consumption, decrease interrupt latency and enable synchronization with external events

Electrical features

  • Supply voltage specified at 1.71 V to 5.25 V
  • Current consumption (core) of 0.15 and 1.5 mA per MHz at 1.89 V and 5.25 V respectively
  • Variable length instruction set, enabling code size optimization over fixed length instruction set processors, results in power savings
  • Fully static circuitry allows stopping the clock to conserve power

The W65C02S may be operated at any convenient supply voltage (VDD) between 1.8 and 5 volts (±5%). The data sheet AC characteristics table lists operational characteristics at 5V/14 MHz, 3.3V/8 MHz, 3V/8 MHz, 2.5V/4 MHz, and 1.8V/2 MHz. This information may be an artifact of an earlier data sheet, as a graph indicates that typical devices are capable of operation at higher speeds than suggested by the AC characteristics table, and that reliable operation at 20MHz should be readily attainable with VDD at 5 volts, assuming the supporting hardware will allow it. WDC has reported that FPGA realizations of the W65C02S have been successfully operated at 200MHz.

The W65C02S may also be operated at non-integral clock rates such as 13.5MHz (digital SDTV luma sampling rate), 14.31818MHz (NTSC colour carrier frequency × 4), 14.75MHz (PAL square pixels), 14.7456 (baud rate crystal), etc, as long as VDD is sufficient to support the frequency. Designer Bill Mensch has pointed out that FMAX is affected by off-chip factors, such as the capacitive load on the microprocessor's pins. Minimising load by using short signal tracks and fewest devices helps raise FMAX. The PLCC and QFP packages have less pin-to-pin capacitance than the PDIP package, and are more economical in the use of printed circuit board space.

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