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AES instruction set


AES instruction set

Advanced Encryption Standard Instruction Set (or the Intel Advanced Encryption Standard New Instructions; AES-NI) is an extension to the x86 instruction set architecture for microprocessors from Intel and AMD proposed by Intel in March 2008.[1] The purpose of the instruction set is to improve the speed of applications performing encryption and decryption using the Advanced Encryption Standard (AES).

New instructions

Instruction Description[2]
AESENC Perform one round of an AES encryption flow
AESENCLAST Perform the last round of an AES encryption flow
AESDEC Perform one round of an AES decryption flow
AESDECLAST Perform the last round of an AES decryption flow
AESKEYGENASSIST Assist in AES round key generation
AESIMC Assist in AES Inverse Mix Columns
PCLMULQDQ Carryless multiply (CLMUL).[3]

Supporting CPUs

  • Intel[4]
    • Intel Westmere based processors, specifically:
    • Intel Sandy Bridge processors:
      • Desktop: all except Pentium, Celeron, Core i3,[5][6]
      • Mobile: all Core i7 and Core i5. Several vendors have shipped BIOS configurations with the extension disabled;[7] a BIOS update is required to enable them.[8]
    • Intel Ivy Bridge processors
      • All i5, i7, Xeon and i3-2115C[9] only.
    • Intel Haswell processors. (all except i3-4000m,[10] Pentium and Celeron)
    • Intel has a list of processors that support AES-NI on their web site[11]
  • AMD


In AES-NI Performance Analyzed, Patrick Schmid and Achim Roos found, "... impressive results from a handful of applications already optimized to take advantage of Intel's AES-NI capability".[13] A performance analysis using the Crypto++ security library showed an increase in throughput from approximately 28.0 cycles per byte to 3.5 cycles per byte with AES/GCM versus a Pentium 4 with no acceleration.[14][15]

Supporting software

The following software is known to support the AES instruction set.


Programming Languages


Hardware acceleration in other architectures

AES support with unprivileged processor instructions is also available in the latest SPARC processors (T4, T5, M5, and forward) and in latest ARM processors. The SPARC T4 processor, introduced in 2011, has user level instructions implementing AES rounds.[34] These instructions are in addition to higher level encryption commands. The ARMv8-A processor architecture, announced in 2011, will also have user level instructions which implement AES rounds.[35] In Aug 2012 IBM announced[36] that the forthcoming Power7+ architecture would have AES support. The commands in these architectures are not directly compatible with the AES-NI commands, but implement similar functionality.

IBM z9 or later mainframe processors support AES as single-opcode (KM, KMC) AES ECB/CBC instructions via IBM's CryptoExpress hardware [37] These single-instruction AES versions are therefore easier to use than Intel NI ones, but may not be extended to implement other algorithms based on AES round functions (such as the Whirlpool hash function).

Supporting CPUs

VIA x86 CPUs, AMD Geode, and Marvell Kirkwood (ARM, mv_cesa in Linux) use driver based accelerated AES handling instead. (see Crypto API (Linux)) The following chips, while supporting AES hardware acceleration, do not support the AES-NI instruction set

See also


  1. ^ "Intel Software Network". Intel. Archived from the original on 7 April 2008. Retrieved 2008-04-05. 
  2. ^ Shay Gueron (2010). "Intel Advanced Encryption Standard (AES) Instruction Set White Paper". Intel. Retrieved 2012-09-20. 
  3. ^ "Carry-Less Multiplication". Intel. 
  4. ^ ARK: Advanced Search
  5. ^ AnandTech - The Sandy Bridge Review: Intel Core i7-2600K, i5-2500K and Core i3-2100 Tested
  6. ^ Compare Intel® Products
  7. ^ AES-NI support in TrueCrypt (Sandy Bridge problem)
  8. ^ "Some products can support AES New Instructions with a Processor Configuration update, in particular, i7-2630QM/i7-2635QM, i7-2670QM/i7-2675QM, i5-2430M/i5-2435M, i5-2410M/i5-2415M. Please contact OEM for the BIOS that includes the latest Processor configuration update.". 
  9. ^ [1]
  10. ^
  11. ^ ARK: Advanced Search
  12. ^ "Following Instructions". AMD. November 22, 2010. Retrieved 2011-01-04. 
  13. ^ P. Schmid and A. Roos (2010). "AES-NI Performance Analyzed". Tom's Hardware. Retrieved 2010-08-10. 
  14. ^ T. Krovetz, W. Dai (2010). "How to get fast AES calls?". Crypto++ user group. Retrieved 2010-08-11. 
  15. ^ "Crypto++ 5.6.0 Pentium 4 Benchmarks". Crypto++ Website. 2009. Archived from the original on 19 September 2010. Retrieved 2010-08-10. 
  16. ^ "Information Security Corp., Cryptographic Development Kits (CDKs)". 
  17. ^ "Intel Advanced Encryption Standard Instructions (AES-NI)". Intel. March 2, 2010. Archived from the original on 7 July 2010. Retrieved 2010-07-11. 
  18. ^ "High-performance cryptography for the JVM". 
  19. ^ "AES-NI enhancements to NSS on Sandy Bridge systems". 2012-05-02. Retrieved 2012-11-25. 
  20. ^ "System Administration Guide: Security Services, Chapter 13 Solaris Cryptographic Framework (Overview)". Oracle. September 2010. Retrieved 2012-11-27. 
  21. ^ "FAQ - Botan". 
  22. ^ Tom's Hardware: AES-NI Performance Analyzed (Benchmark Results: 7-Zip)
  23. ^ Tom's Hardware: Four Compression And Archiving Solutions Compared (7-Zip 9.1 Beta)
  24. ^ Conceal- Encrypting Data just got better
  25. ^ "Mac OS X 10.7 Lion: the Ars Technica review". Ars Technica. 2011-07-20. Retrieved 2012-01-03. 
  26. ^ "Intel and McAfee Endpoint Encryption". Retrieved 2014-03-07. 
  27. ^ "FreeBSD 8.2 Release Notes". 2011-02-24. Retrieved 2011-12-18. 
  28. ^ OpenSSL: CVS Web Interface
  29. ^ "Transparent Data Encryption". Oracle. January 17, 2011. Retrieved 2011-01-17. 
  30. ^ "PGP Desktop 10.1.x for Windows Release Notes".  
  31. ^ "Symantec PGP Desktop 10.2 for Mac OS X Release Notes".  
  32. ^ "Information Security Corp., SecretAgent 6". 
  33. ^ "SecureDoc Full Disk Encryption". April 8, 2011. 
  34. ^ Dan Anderson (2011). "SPARC T4 OpenSSL Engine". Oracle. Retrieved 2012-09-20. 
  35. ^ Richard Grisenthwaite (2011). "ARMv8-A Technology Preview". ARM. Retrieved 2012-09-20. 
  36. ^ Timothy Prickett Morgan (2012). "All the sauce on Big Blue's hot chip: More on Power7+". The Register. Retrieved 2012-09-20. 
  37. ^ "IBM System z10 cryptography". IBM. Retrieved 2014-01-27. 
  38. ^ "AMD Geode™ LX Processor Family Technical Specifications". AMD. 
  39. ^ "VIA Padlock Security Engine". VIA. Retrieved 2011-11-14. 
  40. ^ "VIA Eden-N Processors". VIA. Retrieved 2011-11-14. 
  41. ^ "VIA C7 Processors". VIA. Retrieved 2011-11-14. 
  42. ^ "Using the XMEGA built-in AES accelerator". Retrieved 2014-12-03. 

External links

  • Intel® Advanced Encryption Standard Instructions (AES-NI)
  • AES instruction set whitepaper (4.4 Mbyte, pdf) // Intel
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