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PWRficient

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Title: PWRficient  
Author: World Heritage Encyclopedia
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Subject: AmigaOne X1000, AltiVec, Power Architecture, P.A. Semi, Daniel W. Dobberpuhl
Collection: Power Microprocessors
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PWRficient

PWRficient is the name of a series of microprocessors designed by P.A. Semi where the PA6T-1682M was the only one that became an actual product.

PWRficient processors comply with the 64-bit Power Architecture, and are designed for high performance and extreme power efficiency. The processors are highly modular and can be combined to multi-core system-on-a-chip designs, combining CPU, northbridge, and southbridge functionality on a single processor die.

The PA6T was the first and only processor core from P.A. Semi, and it was offered in two distinct lines of products, 16xxM dual core processors and 13xxM/E single core processors. The PA6T lines differed in their L2 cache size, their memory controllers, their communication functionality, and their cryptography offloading features. At one time, P.A. Semi had plans to offer parts with up to 16 cores.[1]

The PA6T core is the first Power Architecture core to be designed from scratch outside the AIM alliance (i.e. not designed by IBM, Motorola/Freescale, or Apple Inc.) in ten years. Since Texas Instruments was one of the investors in P.A. Semi, it was suggested that their fabrication plants would have been used to manufacture the PWRficient processors.[1]

PWRficient processors were initially shipped to select customers in February 2007 and were released for worldwide sale in Q4 2007.[2]

P.A. Semi was bought by Apple Inc. in April 2008,[3] and closed down development of PWRficient architecture processors. However, it will continue to manufacture, sell and support these components for the foreseeable future due to an agreement with the US Government, as the processors are used in some military applications.[4][5]

Contents

  • Implementation 1
    • CPU 1.1
    • Memory system 1.2
    • I/O 1.3
  • Notable users 2
  • References 3
  • External links 4

Implementation

PA6T-1682M
Produced From 2007 to 2008
Designed by P.A. Semi
Max. CPU clock rate 1.8 GHz to 2.0 GHz
Min. feature size 65 nm
Instruction set Power Architecture (Power ISA v.2.04)
Microarchitecture PA6T
Cores 2
L1 cache 64+64 KB/core
L2 cache 2 MB/core

PWRficient processors comprise three parts:

CPU

PA6T

Memory system

CONEXIUM

I/O

ENVOI

Notable users

References

  1. ^ a b "PA Semi heads to 16 cores on back of $50m boost". The Register. 2006-05-17. Retrieved 2012-07-02. 
  2. ^ "Press release". P.A. Semi. Retrieved 2007-02-07. 
  3. ^ Brown, Erika; Corcoran, Elizabeth; Caulfield, Brian (2008-04-23). "Apple Buys Chip Designer". Forbes. Retrieved 2011-07-05. 
  4. ^ "Apple will please missile makers by backing PA Semi's chip". The Register. 2008-05-16. Retrieved 2011-07-05. 
  5. ^ "DoD may push back on Apple's P.A. Semi bid". EETimes. 2008-05-23. Retrieved 2011-07-05. 
  6. ^ http://pasemi.com/news/pr_2007_12_20a.html
  7. ^ http://www.forbes.com/prnewswire/feeds/prnewswire/2008/02/21/prnewswire200802211030PR_NEWS_USPR_____NETH062.html. 
  8. ^ http://www.theregister.co.uk/2008/01/14/pasemi_takes_nec/
  9. ^ http://a-eon.com/x1000.html

External links

  • Start-up plans new energy-efficient processor
  • PA Semi attacks performance/Watt
  • FPF 2005: P.A. Semi's PA6T-1682M System on a Chip – Real World Technologies
  • Judicious Clocking Subdues Power-Architecture Cooling Needs – Electronic Design
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